#	This is a shell archive.
#	Remove everything above and including the cut line.
#	Then run the rest of the file through sh.
#----cut here-----cut here-----cut here-----cut here----#
#!/bin/sh
# shar:	Shell Archiver
#	Run the following text with /bin/sh to create:
#	README
#	ascu.h
#	ascuLib.c
#	sio1.h
#	sio1Drv.c
# This archive created: Wed Jul 18 07:19:45 1990
echo shar: extracting README '(396 characters)'
sed 's/^X//' << \SHAR_EOF > README
XThese files were contributed by:
X
X	Jim Talbot
X	Force Computers
X	3165 Winchester Blvd.
X	Campbell, CA 95008
X	(408) 370-6300, x233
X
XThey are for the the Force ASCU-2 Advanced System Control Unit 2 and
Xthe Force SIO-1 Serial Input/Output 1 boards. The files in directory
Xfrc21 are configuration and build files for adding these to a Force
XCPU-21 system, but should be easily modified for other cpus.
SHAR_EOF
if test 396 -ne "`wc -c README`"
then
echo shar: error transmitting README '(should have been 396 characters)'
fi
echo shar: extracting ascu.h '(17607 characters)'
sed 's/^X//' << \SHAR_EOF > ascu.h
X/* ascu.h - Force SYS68K/ASCU-2 board header file */
X
X/*
Xmodification history
X--------------------
X01a,16jun87,tja  written
X*/
X
X/*
XDESCRIPTION
XThis file contains IO address and related constants for the Force ASCU board,
Xa high performance system controller which contains powerful i/o devices
Xsuch as a serial interface, a parallel interface, a real time clock with
Xbattery backup, a 4 level bus arbiter, an IEEE 488 GPIB interface (for all
Xyou HP fans), and interrupt capabilities.
X
XNOTE:
XThe define's used here are made not to conflict with the
Xdefine's used in the frc21.h header file. The ASCU board uses
Xthe same set of chips as the CPU-21/9 so care has been taken
Xto eliminate multiple define's or redefining previous define's.
X*/
X
X#ifndef	INCascuh
X#define	INCascuh
X
X#ifndef	ASMLANGUAGE
X
Xstruct rtc	/* real time clock structure */
X    {
X    int month;		/* month 1-12 */
X    int day;		/* day of week 1-7 */
X    int date;		/* day of month 1-31 */
X    int hour;		/* 24 hour 0-23 */
X    int mins;		/* minutes 0-59 */
X    int sec;		/* seconds 0-59 */
X    int s100;		/* hundreds and tenths of seconds */
X    int s10000;		/* ten thousands of seconds */
X    };
X
X#endif	ASMLANGUAGE
X
X
X#define ASCU_CLK_FREQ	8064000	/* frequency of PI/T clock input */
X#define N_PROG_CHANNELS	8	/* no. of programmable IRQ channels */
X#define N_USR_INTS	5	/* no. of user interrupts */
X
X/* The base address for all on-board I/O devices is changeable.
X * Here, the as-shipped address is used.
X */
X
X#define ASCU_BASE ((char *) 0xfcb02000)
X
X/* port addresses for MPCC */
X
X#define AMPCC_RSR        (ASCU_BASE + 0x001)   /* rcvr status reg */
X#define AMPCC_RCR        (ASCU_BASE + 0x021)   /* rcvr control reg */
X#define AMPCC_RDR        (ASCU_BASE + 0x003)   /* rcvr data reg */
X#define AMPCC_RIVNR      (ASCU_BASE + 0x005)   /* rcvr interrupt vec num reg */
X#define AMPCC_RIER       (ASCU_BASE + 0x025)   /* rcvr interrupt enable reg */
X
X#define AMPCC_TSR        (ASCU_BASE + 0x009)   /* xmitter status reg */
X#define AMPCC_TCR        (ASCU_BASE + 0x029)   /* xmitter control reg */
X#define AMPCC_TDR        (ASCU_BASE + 0x00b)   /* xmitter data reg */
X#define AMPCC_TIVNR      (ASCU_BASE + 0x00d)   /* xmitter int vec num reg */
X#define AMPCC_TIER       (ASCU_BASE + 0x02d)   /* xmitter int enable reg */
X
X#define AMPCC_SISR       (ASCU_BASE + 0x011)   /* serial intfc status reg */
X#define AMPCC_SICR       (ASCU_BASE + 0x031)   /* serial intfc control reg */
X#define AMPCC_SIVNR      (ASCU_BASE + 0x015)   /* serial intfc int vec num */
X#define AMPCC_SIER       (ASCU_BASE + 0x035)   /* serial intfc int enable */
X
X#define AMPCC_PSR1       (ASCU_BASE + 0x019)   /* protocol select reg 1 */
X#define AMPCC_PSR2       (ASCU_BASE + 0x039)   /* protocol select reg 2 */
X#define AMPCC_AR1        (ASCU_BASE + 0x01b)   /* address reg 1 */
X#define AMPCC_AR2        (ASCU_BASE + 0x03b)   /* address reg 2 */
X#define AMPCC_BRDR1      (ASCU_BASE + 0x01d)   /* baud rate divider reg 1 */
X#define AMPCC_BRDR2      (ASCU_BASE + 0x03d)   /* baud rate divider reg 2 */
X#define AMPCC_CCR        (ASCU_BASE + 0x01f)   /* clock control reg */
X#define AMPCC_ECR        (ASCU_BASE + 0x03f)   /* error control reg */
X
X
X/* MPCC rcvr status reg bits */
X
X#ifndef MPCC_RSR_RDA
X#define MPCC_RSR_RDA    0x80            /* rcvr data available */
X#define MPCC_RSR_EOF    0x40            /* end of frame */
X#define MPCC_RSR_CPERR  0x10            /* crc/parity error */
X#define MPCC_RSR_FRERR  0x08            /* framing error */
X#define MPCC_RSR_ROVRN  0x04            /* rcvr overrun */
X#define MPCC_RSR_RAB    0x02            /* rcvr abort/break */
X#define MPCC_RSR_RIDLE  0x01            /* rcvr idle */
X
X/* MPCC rcvr control reg bits */
X
X#define MPCC_RCR_RDSREN 0x40            /* rcvr data service req enable */
X#define MPCC_RCR_DONEEN 0x20            /* DONE output enable */
X#define MPCC_RCR_RSYNEN 0x10            /* RSYNEN output enable */
X#define MPCC_RCR_STRSYN 0x08            /* strip SYN char (COP only) */
X#define MPCC_RCR_2ADCMP 0x04            /* 1/2 address compare (BOP only) */
X#define MPCC_RCR_RABTEN 0x02            /* rcvr abort enable (BOP only) */
X#define MPCC_RCR_RRES   0x01            /* rcvr reset command */
X
X/* MPCC rcvr interrupt enable reg bits */
X
X#define MPCC_RIER_RDA   0x80            /* rcvr data available int enable */
X#define MPCC_RIER_EOF   0x40            /* EOF interrupt enable */
X#define MPCC_RIER_CPERR 0x20            /* crc/parity error int enable */
X#define MPCC_RIER_FRERR 0x08            /* frame error int enable */
X#define MPCC_RIER_ROVRN 0x04            /* rcvr overrun int enable */
X#define MPCC_RIER_RAB   0x02            /* rcvr abort/break int enable */
X
X/* MPCC xmitter status reg bits */
X
X#define MPCC_TSR_TDRA   0x80            /* xmit data reg avail */
X#define MPCC_TSR_TFC    0x40            /* xmitted frame complete */
X#define MPCC_TSR_TUNRN  0x04            /* xmitter underrun */
X#define MPCC_TSR_TFERR  0x02            /* xmitter frame error */
X
X/* MPCC xmitter control reg bits */
X
X#define MPCC_TCR_TEN    0x80            /* xmitter enable */
X#define MPCC_TCR_TDSREN 0x40            /* xmitter data service req enable */
X#define MPCC_TCR_TICS   0x20            /* xmitter idle char select */
X#define MPCC_TCR_THW    0x10            /* xmit half word (word mode only) */
X#define MPCC_TCR_TLAST  0x08            /* xmit last char */
X#define MPCC_TCR_TSYN   0x04            /* xmit SYN */
X#define MPCC_TCR_TABT   0x02            /* xmit ABORT */
X#define MPCC_TCR_TRES   0x01            /* xmitter reset command */
X
X/* MPCC xmitter interrupt enable reg bits */
X
X#define MPCC_TIER_TDRA  0x80            /* xmitter data reg avail int enable */
X#define MPCC_TIER_TFC   0x40            /* xmit frame complete int enable */
X#define MPCC_TIER_TUNRN 0x04            /* xmitter underrun int enable */
X#define MPCC_TIER_TFERR 0x02            /* xmitter frame error int enable */
X
X/* MPCC Serial Interface status reg bits - not currently used */
X/* MPCC Serial Interface control reg bits */
X
X#define MPCC_SICR_RTSLVL 0x80           /* Request To Send level */
X#define MPCC_SICR_DTRLVL 0x40           /* Data Terminal Ready level */
X#define MPCC_SICR_ECHO   0x04           /* echo mode enable */
X#define MPCC_SICR_TEST   0x02           /* self-test enable */
X#define MPCC_SICR_NRZI   0x01           /* NRZI data format select */
X
X/* MPCC Serial Interface interrupt enable reg bits - not currently used */
X/* MPCC protocol select reg 1 bits - not currently used */
X/* MPCC protocol select reg 2 bits */
X
X#define MPCC_PSR2_WDBYTE        0x80    /* data bus word/byte */
X
X#define MPCC_PSR2_1STOP         0x00    /* 1 stop bit */
X#define MPCC_PSR2_12STOP        0x20    /* 1 1/2 stop bits */
X#define MPCC_PSR2_2STOP         0x40    /* 2 stop bits */
X
X#define MPCC_PSR2_5BITS         0x00    /* 5-bit chars */
X#define MPCC_PSR2_6BITS         0x08    /* 6-bit chars */
X#define MPCC_PSR2_7BITS         0x10    /* 7-bit chars */
X#define MPCC_PSR2_8BITS         0x18    /* 8-bit chars */
X
X#define MPCC_PSR2_ASYNC         0x06    /* async protocol */
X
X/* MPCC clock control reg bits */
X
X#define MPCC_CCR_PSCDIV         0x10    /* prescaler divider */
X#define MPCC_CCR_TCLKO          0x08    /* xmitter clock output sel */
X#define MPCC_CCR_RCLKIN         0x04    /* select external/internal rx clock */
X#define MPCC_CCR_DIV1           0x00    /* external rx clock divide by 1 */
X#define MPCC_CCR_DIV16          0x01    /* external rx clock divide by 16 */
X#define MPCC_CCR_DIV32          0x02    /* external rx clock divide by 32 */
X#define MPCC_CCR_DIV64          0x03    /* external rx clock divide by 64 */
X
X/* MPCC error control reg bits */
X
X#define MPCC_ECR_PAREN          0x80    /* parity enable */
X#define MPCC_ECR_ODDPAR         0x40    /* odd/even parity select */
X#define MPCC_ECR_CRCCTL         0x08    /* control field CRC enable */
X#define MPCC_ECR_CRCPRE         0x04    /* crc generator preset select */
X#define MPCC_ECR_CRCSEL1        0x00    /* crc polynomial 1 */
X#define MPCC_ECR_CRCSEL2        0x01    /* crc polynomial 2 */
X#define MPCC_ECR_CRCSEL3        0x02    /* crc polynomial 3 */
X#define MPCC_ECR_CRCSEL4        0x03    /* crc polynomial 4 */
X#endif
X
X/* port addresses for PI/T-1 */
X
X#define PIT1_PGCR        (ASCU_BASE + 0x041)    /* port general control reg */
X#define PIT1_PSRR        (ASCU_BASE + 0x043)    /* port service request reg */
X#define PIT1_PADDR       (ASCU_BASE + 0x045)    /* port A data direction reg */
X#define PIT1_PBDDR       (ASCU_BASE + 0x047)    /* port B data direction reg */
X#define PIT1_PCDDR       (ASCU_BASE + 0x049)    /* port C data direction reg */
X#define PIT1_PIVR        (ASCU_BASE + 0x04b)    /* port interrupt vector reg */
X#define PIT1_PACR        (ASCU_BASE + 0x04d)    /* port A control reg */
X#define PIT1_PBCR        (ASCU_BASE + 0x04f)    /* port B control reg */
X#define PIT1_PADR        (ASCU_BASE + 0x051)    /* port A data reg */
X#define PIT1_PBDR        (ASCU_BASE + 0x053)    /* port B data reg */
X#define PIT1_PAAR        (ASCU_BASE + 0x055)    /* port A alternate reg */
X#define PIT1_PBAR        (ASCU_BASE + 0x057)    /* port B alternate reg */
X#define PIT1_PCDR        (ASCU_BASE + 0x059)    /* port C data reg */
X#define PIT1_PSR         (ASCU_BASE + 0x05b)    /* port status reg */
X
X#define PIT1_TCR         (ASCU_BASE + 0x061)   /* timer control reg */
X#define PIT1_TVIR        (ASCU_BASE + 0x063)   /* timer interrupt vector reg */
X#define PIT1_CPRH        (ASCU_BASE + 0x067)   /* counter preload reg high */
X#define PIT1_CPRM        (ASCU_BASE + 0x069)   /* counter preload reg medium */
X#define PIT1_CPRL        (ASCU_BASE + 0x06b)   /* counter preload reg low */
X#define PIT1_CNTRH       (ASCU_BASE + 0x06f)   /* count reg high */
X#define PIT1_CNTRM       (ASCU_BASE + 0x071)   /* count reg medium */
X#define PIT1_CNTRL       (ASCU_BASE + 0x073)   /* count reg low */
X#define PIT1_TSR         (ASCU_BASE + 0x075)   /* timer status reg */
X
X/* port addresses for PI/T-2 */
X
X#define PIT2_PGCR	(ASCU_BASE + 0x081)	/* port general control reg */
X#define PIT2_PSRR	(ASCU_BASE + 0x083)	/* port service request reg */
X#define PIT2_PADDR	(ASCU_BASE + 0x085)	/* port A data direction reg */
X#define PIT2_PBDDR	(ASCU_BASE + 0x087)	/* port B data direction reg */
X#define PIT2_PCDDR	(ASCU_BASE + 0x089)	/* port C data direction reg */
X#define PIT2_PIVR	(ASCU_BASE + 0x08b)	/* port interrupt vector reg */
X#define PIT2_PACR	(ASCU_BASE + 0x08d)	/* port A control reg */
X#define PIT2_PBCR	(ASCU_BASE + 0x08f)	/* port B control reg */
X#define PIT2_PADR	(ASCU_BASE + 0x091)	/* port A data reg */
X#define PIT2_PBDR	(ASCU_BASE + 0x093)	/* port B data reg */
X#define PIT2_PAAR	(ASCU_BASE + 0x095)	/* port A alternate reg */
X#define PIT2_PBAR	(ASCU_BASE + 0x097)	/* port B alternate reg */
X#define PIT2_PCDR	(ASCU_BASE + 0x099)	/* port C data reg */
X#define PIT2_PSR	(ASCU_BASE + 0x09b)	/* port status reg */
X
X#define PIT2_TCR         (ASCU_BASE + 0x0a1)	/* timer control reg */
X#define PIT2_TVIR        (ASCU_BASE + 0x0a3)	/* timer interrupt vector reg */
X#define PIT2_CPRH        (ASCU_BASE + 0x0a7)	/* counter preload reg high */
X#define PIT2_CPRM        (ASCU_BASE + 0x0a9)	/* counter preload reg medium */
X#define PIT2_CPRL        (ASCU_BASE + 0x0ab)	/* counter preload reg low */
X#define PIT2_CNTRH       (ASCU_BASE + 0x0af)	/* count reg high */
X#define PIT2_CNTRM       (ASCU_BASE + 0x0b1)	/* count reg medium */
X#define PIT2_CNTRL       (ASCU_BASE + 0x0b3)	/* count reg low */
X#define PIT2_TSR         (ASCU_BASE + 0x0b5)	/* timer status reg */
X
X
X/* PI/T timer status register bits */
X
X#ifndef	PIT_TSR_ZDS
X#define	PIT_TSR_ZDS             0x01            /* zero detect status */
X
X/* PI/T timer control reg bits */
X
X#define PIT_TCR_TOUT0	0x00	/* TOUT/TIACK ctrl 0 */
X#define PIT_TCR_TOUT2	0x40	/* TOUT/TIACK ctrl 2 */
X#define PIT_TCR_TOUT4	0x80	/* TOUT/TIACK ctrl 4 */
X#define PIT_TCR_TOUT5	0xa0	/* TOUT/TIACK ctrl 5 */
X#define PIT_TCR_TOUT6	0xc0	/* TOUT/TIACK ctrl 6 */
X#define PIT_TCR_TOUT7	0xd0	/* TOUT/TIACK ctrl 7 */
X#define PIT_TCR_ZDC	0x10	/* zero detect control */
X#define PIT_TCR_CC0	0x00	/* clock control 0 */
X#define PIT_TCR_CC1	0x02	/* clock control 0 */
X#define PIT_TCR_CC2	0x04	/* clock control 0 */
X#define PIT_TCR_CC3	0x06	/* clock control 0 */
X#define PIT_TCR_TEN	0x01	/* timer enable */
X
X#endif	PIT_TSR_ZDS
X
X/* port addresses for RTC */
X
X#define RTC_CTR_10000	(ASCU_BASE + 0x0c1)	/* counter, 1/10000 sec */
X#define RTC_CTR_100	(ASCU_BASE + 0x0c3)	/* counter, 1/100 & 1/10 sec */
X#define RTC_CTR_1	(ASCU_BASE + 0x0c5)	/* counter, 1 sec */
X#define RTC_CTR_MIN	(ASCU_BASE + 0x0c7)	/* counter, minutes */
X#define RTC_CTR_HOUR	(ASCU_BASE + 0x0c9)	/* counter, hours */
X#define RTC_CTR_DAY	(ASCU_BASE + 0x0cb)	/* counter, day of week */
X#define RTC_CTR_DATE	(ASCU_BASE + 0x0cd)	/* counter, day of month */
X#define RTC_CTR_MONTH	(ASCU_BASE + 0x0cf)	/* counter, month */
X#define RTC_RAM_10000	(ASCU_BASE + 0x0d1)	/* counter, 1/10000 sec */
X#define RTC_RAM_100	(ASCU_BASE + 0x0d3)	/* counter, 1/10 & 1/10 sec */
X#define RTC_RAM_1	(ASCU_BASE + 0x0d5)	/* counter, 1 sec */
X#define RTC_RAM_MIN	(ASCU_BASE + 0x0d7)	/* counter, minutes */
X#define RTC_RAM_HOUR	(ASCU_BASE + 0x0d9)	/* counter, hours */
X#define RTC_RAM_DAY	(ASCU_BASE + 0x0db)	/* counter, day of week */
X#define RTC_RAM_DATE	(ASCU_BASE + 0x0dd)	/* counter, day of month */
X#define RTC_RAM_MONTH	(ASCU_BASE + 0x0df)	/* counter, month */
X#define RTC_ISR		(ASCU_BASE + 0x0e1)	/* interrupt status reg */
X#define RTC_ICR		(ASCU_BASE + 0x0e3)	/* interrupt control reg */
X#define RTC_CTR_RESET	(ASCU_BASE + 0x0e5)	/* counter reset */
X#define RTC_RAM_RESET	(ASCU_BASE + 0x0e7)	/* RAM reset */
X#define RTC_STATUS	(ASCU_BASE + 0x0e9)	/* status bit */
X#define RTC_GO		(ASCU_BASE + 0x0eb)	/* GO command */
X#define RTC_STANDBY_INT	(ASCU_BASE + 0x0ed)	/* standby-interrupt */
X#define RTC_TEST	(ASCU_BASE + 0x0ff)	/* test mode */
X
X/* bit values for RTC interrupt control and status registers */
X
X#define RTC_IR_COMPARE		0x01		/* RAM compare interrupt */
X#define RTC_IR_10		0x02		/* 10Hz interrupt */
X#define RTC_IR_1		0x04		/* 1 Hz interrupt */
X#define RTC_IR_MIN		0x08		/* 1/Minute int */
X#define RTC_IR_HOUR		0x10		/* 1/Hour int */
X#define RTC_IR_DAY		0x20		/* 1/Day int */
X#define RTC_IR_WEEK		0x40		/* 1/Week int */
X#define RTC_IR_MONTH		0x80		/* 1/Month int */
X
X/* port addresses for GPIB controller */
X
X#define GPIB_DATAIN	(ASCU_BASE + 0x141)	/* r/o data in */
X#define GPIB_INTS1	(ASCU_BASE + 0x143)	/* r/o interrupt status 1 */
X#define GPIB_INTS2	(ASCU_BASE + 0x145)	/* r/o interrupt status 2 */
X#define GPIB_SERPS	(ASCU_BASE + 0x147)	/* r/o serial poll status */
X#define GPIB_ADDRS	(ASCU_BASE + 0x149)	/* r/o address status */
X#define GPIB_COMPT	(ASCU_BASE + 0x14b)	/* r/o command pass thru */
X#define GPIB_ADDR0	(ASCU_BASE + 0x14d)	/* r/o address 0 */
X#define GPIB_ADDR1	(ASCU_BASE + 0x14f)	/* r/o address 1 */
X
X#define GPIB_BYTEO	(ASCU_BASE + 0x141)	/* w/o byte out */
X#define GPIB_INTM1	(ASCU_BASE + 0x143)	/* w/o interrupt mask 1 */
X#define GPIB_INTM2	(ASCU_BASE + 0x145)	/* w/o interrupt mask 2 */
X#define GPIB_SERPM	(ASCU_BASE + 0x147)	/* w/o serial poll mask */
X#define GPIB_ADDRM	(ASCU_BASE + 0x149)	/* w/o address mode */
X#define GPIB_AUXM	(ASCU_BASE + 0x14b)	/* w/o auxiliary mode */
X#define GPIB_ADDR01	(ASCU_BASE + 0x14d)	/* w/o address 0/1 */
X#define GPIB_EOS	(ASCU_BASE + 0x14f)	/* w/o end of string */
X
X/* port addresses for BIM-1 */
X
X#define BIM1_CR1	(ASCU_BASE + 0x101)	/* control reg 1 */
X#define BIM1_CR2	(ASCU_BASE + 0x103)	/* control reg 2 */
X#define BIM1_CR3	(ASCU_BASE + 0x105)	/* control reg 3 */
X#define BIM1_CR4	(ASCU_BASE + 0x107)	/* control reg 4 */
X#define BIM1_VR1	(ASCU_BASE + 0x109)	/* vector reg 1 */
X#define BIM1_VR2	(ASCU_BASE + 0x10b)	/* vector reg 2 */
X#define BIM1_VR3	(ASCU_BASE + 0x10d)	/* vector reg 3 */
X#define BIM1_VR4	(ASCU_BASE + 0x10f)	/* vector reg 4 */
X
X/* port addresses for BIM-2 */
X
X#define BIM2_CR1	(ASCU_BASE + 0x111)	/* control reg 1 */
X#define BIM2_CR2	(ASCU_BASE + 0x113)	/* control reg 2 */
X#define BIM2_CR3	(ASCU_BASE + 0x115)	/* control reg 3 */
X#define BIM2_CR4	(ASCU_BASE + 0x117)	/* control reg 4 */
X#define BIM2_VR1	(ASCU_BASE + 0x119)	/* vector reg 1 */
X#define BIM2_VR2	(ASCU_BASE + 0x11b)	/* vector reg 2 */
X#define BIM2_VR3	(ASCU_BASE + 0x11d)	/* vector reg 3 */
X#define BIM2_VR4	(ASCU_BASE + 0x11f)	/* vector reg 4 */
X
X/* port addresses for BIM-3 */
X
X#define BIM3_CR1	(ASCU_BASE + 0x121)	/* control reg 1 */
X#define BIM3_CR2	(ASCU_BASE + 0x123)	/* control reg 2 */
X#define BIM3_CR3	(ASCU_BASE + 0x125)	/* control reg 3 */
X#define BIM3_CR4	(ASCU_BASE + 0x127)	/* control reg 4 */
X#define BIM3_VR1	(ASCU_BASE + 0x129)	/* vector reg 1 */
X#define BIM3_VR2	(ASCU_BASE + 0x12b)	/* vector reg 2 */
X#define BIM3_VR3	(ASCU_BASE + 0x12d)	/* vector reg 3 */
X#define BIM3_VR4	(ASCU_BASE + 0x12f)	/* vector reg 4 */
X
X/* port addresses for BIM-4 */
X
X#define BIM4_CR1	(ASCU_BASE + 0x131)	/* control reg 1 */
X#define BIM4_CR2	(ASCU_BASE + 0x133)	/* control reg 2 */
X#define BIM4_CR3	(ASCU_BASE + 0x135)	/* control reg 3 */
X#define BIM4_CR4	(ASCU_BASE + 0x137)	/* control reg 4 */
X#define BIM4_VR1	(ASCU_BASE + 0x139)	/* vector reg 1 */
X#define BIM4_VR2	(ASCU_BASE + 0x13b)	/* vector reg 2 */
X#define BIM4_VR3	(ASCU_BASE + 0x13d)	/* vector reg 3 */
X#define BIM4_VR4	(ASCU_BASE + 0x13f)	/* vector reg 4 */
X
X/* BIM control reg bits */
X
X#ifndef	BIM_IRE
X
X#define BIM_IRE		0x10		/* interrupt enable */
X#define BIM_IRAC	0x08		/* interrupt auto-clear */
X#define BIM_XIN		0x20		/* don't supply vector */
X#define BIM_F		0x80		/* user-defined flag */
X#define BIM_FAC		0x40		/* clear flag in interrupt */
X
X#endif	BIM_IRE
X
X#endif	INCascuh
SHAR_EOF
if test 17607 -ne "`wc -c ascu.h`"
then
echo shar: error transmitting ascu.h '(should have been 17607 characters)'
fi
echo shar: extracting ascuLib.c '(8483 characters)'
sed 's/^X//' << \SHAR_EOF > ascuLib.c
X/* ascuLib.c - Force SYS68K/CPU-21/9 ASCU2 library */
X
Xstatic char *copyright = "Copyright 1988, Wind River Systems, Inc.";
X
X/*
Xmodification history
X--------------------
X02k,11jul88,gae  written based on Terry Arden's frc21/9 version.
X	   +tja  untested at WRS.
X*/
X
X/*
XDESCRIPTION
XThis library contains a set of routines to manipulate the Force ASCU2 board.
X
XBUGS
XUnknown.  Unused and untested at Wind River Systems.
X*/
X
X/* LINTLIBRARY */
X
X#include "vxWorks.h"
X#include "iv68k.h"
X#include "ascu.h"
X
X
XLOCAL BOOL sysAscu2 = FALSE;
XLOCAL FUNCPTR usrFunc [N_USR_INTS];
XLOCAL int usrArg [N_USR_INTS];
X
XLOCAL char *ascuErrMsg = "%s: not available\n";
X
X
X/* This is a control register table for the BIM controllers
X * which reside on the ASCU2 board.
X */
X
XLOCAL char *ascuBimCtr [] =
X    { BIM3_CR1, BIM3_CR2, BIM3_CR3, BIM3_CR4,
X      BIM4_CR1, BIM4_CR2, BIM4_CR3, BIM4_CR4
X    };
X
X/* This is a vector register table for the BIM controllers
X * which reside on the ASCU2 board.
X */
X
XLOCAL char *ascuBimVec [] =
X    { BIM3_VR1, BIM3_VR2, BIM3_VR3, BIM3_VR4,
X      BIM4_VR1, BIM4_VR2, BIM4_VR3, BIM4_VR4
X    };
X
X
X/* forward declarations */
X
XLOCAL VOID ascuInt ();
X
X
X/*******************************************************************************
X*
X* ascuReset - generate a sysReset on VMEbus
X*/
X
XVOID ascuReset ()
X
X    {
X    if (!sysAscu2)
X	*PIT1_PBDR &= 0x7f;
X    else
X	logMsg (ascuErrMsg, "ascuReset");
X    }
X/*******************************************************************************
X*
X* ascuInit - initialize ASCU2
X*/
X
XVOID ascuInit ()
X
X    {
X    unsigned int wdog;
X    char zero = 0;
X    char probe;
X
X    sysAscu2 = vxMemProbe (AMPCC_RSR, READ, 1, &probe) == OK;
X
X    if (sysAscu2 && sysProcNumGet () == 0)
X	{
X	/* if proc 0, initialize ASCU2 board */
X
X	/* init PI/T-1 to bit I/O mode */
X
X	*PIT1_PGCR &= 0x3f; 	/* Set mode=0, uni-8-bit */
X	*PIT1_PSRR  = 0x18;  	/* PC5 = PIRQ, PC6 = PIACK */
X	*PIT1_PACR |= 0x80;	/* submode=1X, port A */
X	*PIT1_PBCR |= 0x86;	/* submode=1X, port B */
X				/* h3,h4 interrupt enable */
X
X	*PIT1_PBDR  = 0xee;	/* BUS TIMER set to 32us DATA */
X	*PIT1_PBDDR = 0xdf;	/* and IACK-cycle */
X
X	wdog = 0x1000;		/* setup WATCHDOG counter */
X	*PIT2_CPRL  = wdog;	/* for BCLR* Timer */
X	*PIT2_CPRM  = wdog >> 8;
X	*PIT2_CPRH  = wdog >> 16;
X
X	*PIT2_PCDR  = 0xfd;	/* BCLR-mode selection */
X	*PIT2_PCDDR = 0x5b;
X
X	/* init PI/T-2 to bit I/O mode for programmable IRQ-generation 
X	 * and user-defined interrupts.
X	 */
X
X	*PIT2_PGCR &= 0x3f;	/* Set mode=0, uni-8-bit */
X	*PIT2_PSRR  = 0x08;	/* PC5 = PIRQ */
X	*PIT2_PACR |= 0x86;	/* submode=1X, port A */
X				/* h1,h2 interrupt enable */
X	*PIT2_PBCR |= 0x86;	/* submode=1X, port B */
X				/* h3,h4 interrupt enable */
X	*PIT2_PADR  = zero;	/* port A = output */
X	*PIT2_PADDR = 0xff;	/* port A = low */
X
X	/* enable user-defined interrupts */
X
X	*PIT1_PGCR |= 0x20;	/* enable h3,h4 */
X	*PIT2_PGCR |= 0x30;	/* enable h1,h2,h3,h4 */
X	}
X    }
X/*******************************************************************************
X*
X* ascuIntGen - generate VME bus interrupt
X*
X* This routine generates a VME interrupt request at the given
X* IRQ level and vector.
X*
X* RETURNS: OK or ERROR if ASCU2 not present
X*/
X
XSTATUS ascuIntGen (level, vector)
X    FAST int level;
X    FAST int vector;
X
X    {
X    FAST char **csr;
X    FAST char **vec;
X    FAST int i;
X    FAST int found = FALSE;
X
X    if (!sysAscu2) 
X	{
X	logMsg (ascuErrMsg, "ascuIntGen");
X	return (ERROR);
X	}
X
X    /* find a free channel to use */
X
X    while (!found)
X	{
X	csr = ascuBimCtr;
X	vec = ascuBimVec;
X
X	for (i = 0; i < N_PROG_CHANNELS; i++, csr++, vec++)
X	    {
X	    /* test-and-set flat bit of channel */
X	    if (!vxTas (**csr))
X		{
X		found = TRUE;
X		break;
X		}
X	    }
X	}
X
X    **vec = vector;		/* set vector up */
X    **csr = 0xd8 | level;	/* set channel in use and generate IRQ */
X
X    return (OK);
X    }
X/*******************************************************************************
X*
X* ascuRTCSet - set real-time clock
X*
X* RETURNS: OK if ASCU2 present, otherwise ERROR
X*/
X
XSTATUS ascuRTCSet (pRtc)
X    struct rtc *pRtc;
X
X    {
X    if (!sysAscu2)
X	{
X	logMsg (ascuErrMsg, "ascuSetRTC");
X	return (ERROR);
X	}
X
X    *RTC_CTR_RESET	= 0xff;
X    taskDelay (1);
X
X    *RTC_CTR_1		= itobcd (pRtc->sec);
X    taskDelay (1);
X    *RTC_CTR_MIN	= itobcd (pRtc->mins);
X    taskDelay (1);
X    *RTC_CTR_HOUR	= itobcd (pRtc->hour);
X    taskDelay (1);
X    *RTC_CTR_DATE	= itobcd (pRtc->date);
X    taskDelay (1);
X    *RTC_CTR_DAY	= itobcd (pRtc->day);
X    taskDelay (1);
X    *RTC_CTR_MONTH	= itobcd (pRtc->month);
X    taskDelay (1);
X    *RTC_GO;
X
X    return (OK);
X    }
X/*******************************************************************************
X*
X* ascuRTCGet - get time from real-time clock
X*
X* RETURNS: OK if ASCU2 present, otherwise ERROR
X*/
X
XSTATUS ascuRTCGet (pRtc)
X    struct rtc *pRtc;
X
X    {
X    if (!sysAscu2)
X	{
X	logMsg (ascuErrMsg, "ascuRTCGet");
X	return (ERROR);
X	}
X
X    pRtc->s10000	= bcdtoi(*RTC_CTR_10000);
X    taskDelay (1);
X    pRtc->s100		= bcdtoi(*RTC_CTR_100);
X    taskDelay (1);
X    pRtc->sec		= bcdtoi(*RTC_CTR_1);
X    taskDelay (1);
X    pRtc->mins		= bcdtoi(*RTC_CTR_MIN);
X    taskDelay (1);
X    pRtc->hour		= bcdtoi(*RTC_CTR_HOUR);
X    taskDelay (1);
X    pRtc->date		= bcdtoi(*RTC_CTR_DATE);
X    taskDelay (1);
X    pRtc->day		= bcdtoi(*RTC_CTR_DAY);
X    taskDelay (1);
X    pRtc->month		= bcdtoi(*RTC_CTR_MONTH);
X
X    return (OK);
X    }
X/************************************************************************
X*
X* ascuInit - initializes user interrupts for ASCU2
X*
X* This routine enables the specified interrupt and allows user routines
X* to be connected via ascuConnect (2).
X*
X* RETURNS:
X*   OK if ASCU2 present and able to connect to interrupt, otherwise ERROR
X*
X* SEE ALSO: ascuConnect (2)
X*/
X
XSTATUS ascuIntEnable (vecnum, level)
X    int vecnum;		/* vector number */
X    int level;		/* interrupt level */
X
X    {
X    if (!sysAscu2)
X	{
X        logMsg (ascuErrMsg, "ascuInit");
X        return (ERROR);
X	}
X
X    *BIM1_CR1  = BIM_FAC|BIM_IRE|level;
X    *BIM1_VR1  = vecnum;
X
X    return (intConnect (INUM_TO_IVEC (vecnum), ascuInt, 0));
X    }
X/*******************************************************************************
X*
X* ascuConnect - connect interrupt routine to ASCU2 given user interrupt 
X*
X* RETURNS: OK or ERROR
X*
X* SEE ALSO: ascuIntEnable (2)
X*/
X
XSTATUS ascuConnect (intNum, routine, arg)
X    int intNum;		/* user interrupt number (0 thru N_USR_INTS) */
X    FUNCPTR routine;	/* routine to be called */
X    int arg;		/* argument to be passed to routine */
X
X    {
X    if (!sysAscu2)
X	{
X	logMsg (ascuErrMsg, "ascuConnect");
X	return (ERROR);
X	}
X
X    if (intNum < 0 || intNum >= N_USR_INTS)
X	{
X	logMsg ("ascuConnect: invalid user interrupt %d\n", intNum);
X	return (ERROR);
X	}
X
X    usrFunc [intNum] = routine;
X    usrArg [intNum]  = arg;
X
X    return (OK);
X    }
X/*******************************************************************************
X*
X* ascuInt - route user interrupt to user-defined interrupt handler
X*/
X
XLOCAL VOID ascuInt ()
X
X    {
X    FAST int ix;
X    FAST int mask;
X    FAST int *arg = usrArg;
X
X    /* check user interrupt handshake status to determine interrupt source */
X
X    if (*PIT1_PSR & 0x80)
X	{
X	*PIT1_PSR |= 0x80;
X	/* XXX huh? */
X	(*usrFunc[0])(*arg++);
X	}
X
X    for (ix = 1, mask = 1; ix < N_USR_INTS; ix++, mask <<= 1)
X	{
X	if (*PIT2_PSR & mask)
X	    {
X	    *PIT2_PSR |= mask;
X	    /* XXX huh? */
X	    (*usrFunc[ix])(*arg++);
X	    }
X	}
X    }
X
X/*******************************************************************************
X*
X* bcdtoi - convert Binary Coded Decimal byte to an integer
X*
X* This routine converts the specified BCD byte to an integer.
X* Result is unspecified if bcd contains other than a two digit BCD number.
X* Thus:
X*
X*	bcdtoi (0x12) == 12
X*	bcdtoi (0x1a) == something weird
X*
X* RETURNS: integer equivalent of specified bcd
X*/
X
Xint bcdtoi (bcd)
X    UTINY bcd;		/* two BCD digits to be converted */
X
X    {
X    return ((bcd & 0x0f) + (10 * (int)((bcd >> 4) & 0x0f)));
X    }
X/*******************************************************************************
X*
X* itobcd - convert integer to Binary Coded Decimal
X*
X* This routine returns the BCD equivalent of the specified number.
X* Result is undetermined if number not in range 0..9999.
X*
X* RETURNS: four digit BCD equivalent of number
X*/
X
Xint itobcd (number)
X    FAST short number;	/* integer number to convert */
X
X    {
X    FAST short i = 0;
X    FAST short bcd = 0;
X
X    while (number != 0)
X	{
X	bcd |= (number % 10) << i;
X
X	number /= 10;
X	i += 4;
X	}
X
X    return (bcd);
X    }
SHAR_EOF
if test 8483 -ne "`wc -c ascuLib.c`"
then
echo shar: error transmitting ascuLib.c '(should have been 8483 characters)'
fi
echo shar: extracting sio1.h '(2758 characters)'
sed 's/^X//' << \SHAR_EOF > sio1.h
X/* sio1.h - Force SYS68K/SIO-1 board header file */
X
X/*
XModification History
X--------------------
X01a,20Jan89,JWT  Added SIO-1 board to card cage with CPU-21
X01b,13Feb89,JWT  Added capability to separate SIO-1 MPCCs
X*/
X
X#ifndef	INCsio1h
X#define	INCsio1h
X
X/* SIO-1 definitions - byte mode */
X#define SIO1_MPCC_SIZE   0x40                   /* MPCC Register Address Space */
X#define SIO1_MPCCS       6                      /* MPCC channels on SIO-1 */
X#define INT_VEC_SIO1     71                     /* SIO-1 Interrupt Vectors */
X                                                /* 6 consecutive vectors */
X
X#define SIO1_BASE        ((char *) 0x80800000)  /* SIO-1 Base Address */
X#define SIO1_MPCC1_BASE (SIO1_BASE)
X#define SIO1_MPCC2_BASE (SIO1_MPCC1_BASE + SIO1_MPCC_SIZE)
X#define SIO1_MPCC3_BASE (SIO1_MPCC2_BASE + SIO1_MPCC_SIZE)
X#define SIO1_MPCC4_BASE (SIO1_MPCC3_BASE + SIO1_MPCC_SIZE)
X#define SIO1_MPCC5_BASE (SIO1_MPCC4_BASE + SIO1_MPCC_SIZE)
X#define SIO1_MPCC6_BASE (SIO1_MPCC5_BASE + SIO1_MPCC_SIZE)
X
X/* Receiver Registers */
X#define SIO1_MPCC_RSR(base)	((char*) (base) + 0x01)	/* status reg */
X#define SIO1_MPCC_RCR(base)	((char*) (base) + 0x21)	/* control reg */
X#define SIO1_MPCC_RDR(base)	((char*) (base) + 0x03)	/* data reg */
X#define SIO1_MPCC_RIVNR(base)	((char*) (base) + 0x05)	/* int vec num reg */
X#define SIO1_MPCC_RIER(base)	((char*) (base) + 0x25)	/* int enable reg */
X
X/* Transmitter Registers */
X#define SIO1_MPCC_TSR(base)	((char*) (base) + 0x09)	/* status reg */
X#define SIO1_MPCC_TCR(base)	((char*) (base) + 0x29)	/* control reg */
X#define SIO1_MPCC_TDR(base)	((char*) (base) + 0x0B)	/* data reg */
X#define SIO1_MPCC_TIVNR(base)	((char*) (base) + 0x0D)	/* int vec num reg */
X#define SIO1_MPCC_TIER(base)	((char*) (base) + 0x2D)	/* int enable reg */
X
X/* Serial Registers */
X#define SIO1_MPCC_SISR(base)	((char*) (base) + 0x11)	/* intfc status reg */
X#define SIO1_MPCC_SICR(base)	((char*) (base) + 0x31)	/* intfc control reg */
X#define SIO1_MPCC_SIVNR(base)	((char*) (base) + 0x15)	/* intfc int vec num */
X#define SIO1_MPCC_SIER(base)	((char*) (base) + 0x35)	/* intfc int enable */
X
X/* Global Registers */
X#define SIO1_MPCC_PSR1(base)	((char*) (base) + 0x19)	/* protocol sel reg 1 */
X#define SIO1_MPCC_PSR2(base)	((char*) (base) + 0x39)	/* protocol sel reg 2 */
X#define SIO1_MPCC_AR1(base)	((char*) (base) + 0x1B)	/* address reg 1 */
X#define SIO1_MPCC_AR2(base)	((char*) (base) + 0x3B)	/* address reg 2 */
X#define SIO1_MPCC_BRDR1(base)	((char*) (base) + 0x1D)	/* baud rate div reg 1*/
X#define SIO1_MPCC_BRDR2(base)	((char*) (base) + 0x3D)	/* baud rate div reg 2*/
X#define SIO1_MPCC_CCR(base)	((char*) (base) + 0x1F)	/* clock control reg */
X#define SIO1_MPCC_ECR(base)	((char*) (base) + 0x3F)	/* error control reg */
X
X#endif	INCsio1h
SHAR_EOF
if test 2758 -ne "`wc -c sio1.h`"
then
echo shar: error transmitting sio1.h '(should have been 2758 characters)'
fi
echo shar: extracting sio1Drv.c '(12769 characters)'
sed 's/^X//' << \SHAR_EOF > sio1Drv.c
X/* sio1Drv.c - Force SYS68K/SIO-1 MPCC tty handler */
X
Xstatic char *copyright = "Copyright 1988, Wind River Systems, Inc.";
Xstatic char *Force_Copyright = "Copyright 1989, Force Computers, Inc.";
X
X/*
Xmodification history
X--------------------
X01a,24Jan89,JWT Modified tyCoDrv.c to add TTY drivers for SIO-1 board
X*/
X
X/*
XDESCRIPTION
XThis is the driver for the Force SYS68K/SIO-1 serial ports.
X
XUSER CALLABLE ROUTINES
XMost of the routines in this driver are accessible only through the I/O
Xsystem.  Two routines, however, must be called directly, sio1Drv() to
Xinitialize the driver, and sio1DevCreate() to create devices.
X
XSIO1DRV
XBefore using the driver, it must be created by calling the routine:
X
X    sio1Drv ()
X
XThis routine should be called exactly once, before any reads, writes, or
Xsio1DevCreates.  Normally, it is called from usrRoot.
X
XCREATING TERMINAL DEVICES
XBefore a terminal can be used, it must be created.  This is done with the 
Xsio1DevCreate call.  Each port to be used should have exactly one device 
Xassociated with it, by calling this routine.
X
X    STATUS sio1DevCreate (name, channel, rdBufSize, wrtBufSize)
X    char *name;     /* Name to use for this device *
X    int channel;    /* Physical channel for this device (0 or 1) *
X    int rdBufSize;  /* Read buffer size, in bytes *
X    int wrtBufSize; /* Write buffer size, in bytes *
X
XFor instance, to create the device "/sio1/0", with buffer sizes of 512 bytes,
Xthe proper call would be:
X
X   sio1DevCreate ("/sio1/0", 0, 512, 512);
X
XIOCTL
XThis driver responds to all the same ioctl codes as a normal ty driver.
XThe baud rates available are 50, 110, 134, 200, 300, 600, 1200, 1050,
X2400, 4800, 7200, 9600, 38400.
X*/
X
X#include "vxWorks.h"
X#include "ioLib.h"
X#include "iosLib.h"
X#include "tyLib.h"
X#include "frc21.h"
X#include "iv68k.h"
X#include "r68561.h"
X#include "sio1.h"
X
X
XIMPORT int tyRead ();
XIMPORT int tyWrite ();
X
Xtypedef struct          /* TY_CO_DEV */
X    {
X    TY_DEV tyDev;
X    BOOL created;	/* TRUE = device already created */
X    char *mpcc;		/* address of MPCC base */
X    } TY_CO_DEV;
X
XLOCAL TY_CO_DEV sio1Dv[SIO1_MPCCS] = /* device descriptor */
X    {
X    {{{{NULL}}}, FALSE, SIO1_MPCC_BASE_1},
X    {{{{NULL}}}, FALSE, SIO1_MPCC_BASE_2},
X    {{{{NULL}}}, FALSE, SIO1_MPCC_BASE_3},
X    {{{{NULL}}}, FALSE, SIO1_MPCC_BASE_4},
X    {{{{NULL}}}, FALSE, SIO1_MPCC_BASE_5},
X    {{{{NULL}}}, FALSE, SIO1_MPCC_BASE_6}
X    };
X
XLOCAL int sio1DrvNum;      /* driver number assigned to this driver */
X
X/* forward declarations */
XLOCAL VOID sio1Startup ();
XLOCAL int sio1Open ();
XLOCAL STATUS sio1Ioctl ();
XLOCAL VOID sio1Int ();
X
X
X/*******************************************************************************
X*
X* sio1Drv - ty driver initialization routine
X*
X* This routine initializes the serial driver, sets up interrupt vectors,
X* and performs hardware initialization of the serial ports.
X*
X* This routine must be called in supervisor state, since it does
X* physical I/O directly.
X*/
X
XSTATUS sio1Drv ()
X
X    {
X    /* the Force board uses a Bus Interruptor Module to handle
X     * on-board interrupts. A single vectored interrupt is generated
X     * for the console MPCC and a single vectored interrupt is
X     * generated for the slave MPCC unit by using a Parallel
X     * Interface/Timer port. These vectors call a general 
X     * interrupt handler to poll interrupt status bits and
X     * call the appropriate handler. */
X
X    /* The 6 SIO-1 MPCC interrupts are all routed to one common IRQ* signal 
X       across the VMEbus.  The jumper selectable IRQ* level is 4 by default. */
X
X    (void) intConnect (INUM_TO_IVEC (INT_VEC_SIO1),  sio1Int, 0);
X
X    sio1HrdInit ();
X
X    sio1DrvNum = iosDrvInstall (sio1Open, (FUNCPTR) NULL, sio1Open,
X				(FUNCPTR) NULL, tyRead, tyWrite, sio1Ioctl);
X
X    return (sio1DrvNum == ERROR ? ERROR : OK);
X    }
X
X
X/*******************************************************************************
X*
X* sio1DevCreate - create a device for the SIO-1 ports
X*
X* This routine creates a device on one of the serial ports.  Each port
X* to be used should have exactly one device associated with it, by calling
X* this routine.
X*/
X
XSTATUS sio1DevCreate (name, channel, rdBufSize, wrtBufSize)
X    char *name;     /* Name to use for this device */
X    int channel;    /* Physical channel for this device (0 to 5) */
X    int rdBufSize;  /* Read buffer size, in bytes */
X    int wrtBufSize; /* Write buffer size, in bytes */
X
X    {
X    if (sio1DrvNum <= 0)
X	{
X	errnoSet (S_ioLib_NO_DRIVER);
X	return (ERROR);
X	}
X
X    if (sio1Dv[channel].created)
X	return (ERROR);
X
X    /* initialize the ty descriptor */
X
X    if (tyDevInit (&sio1Dv[channel].tyDev,
X		   rdBufSize, wrtBufSize, sio1Startup) != OK)
X	return (ERROR);
X
X    /* Mark the device as having been created, and add the device to
X     * the I/O system */
X
X    sio1Dv[channel].created = TRUE;
X    return (iosDevAdd (&sio1Dv[channel].tyDev.devHdr, name, sio1DrvNum));
X    }
X
X
X/*******************************************************************************
X*
X* sio1HrdInit - initialize the MPCCs on the SIO-1
X*
X* This routine initializes the Force SIO-1 MPCCs for the VxWorks environment.
X*
X* This routine must be called in supervisor mode, since it accesses I/O space.
X*/
X
XLOCAL VOID sio1HrdInit ()
X
X    {
X    int i;
X    int oldlevel;       /* current interrupt level mask */
X    char zero = 0;
X    TY_CO_DEV *ty;
X    FAST char *mpcc;
X
X    oldlevel = intLock ();   /* disable interrupts during init */
X
X    for (i = 0; i < SIO1_MPCCS; i++) 
X	{
X	/* setup pointer to ty device */
X
X	ty = &sio1Dv[i];
X	mpcc = ty->mpcc;
X
X	/* Reset the MPCC, xmitter and rcvr. Then clear resets. */
X	*SIO1_MPCC_RCR (mpcc) = MPCC_RCR_RRES;
X	*SIO1_MPCC_TCR (mpcc) = MPCC_TCR_TRES;
X	*SIO1_MPCC_RCR (mpcc) = zero;		/* clear the reset */
X	*SIO1_MPCC_TCR (mpcc) = zero;		/* clear the reset */
X
X	/* Set up the MPCC global regs. Set up protocol reg for
X	 * 8 data bits, 1 stop bit. Clock control reg for local clock,
X	 * divide by 3 prescaler. Error control reg for no parity.
X	 * Initialize to 9600 baud. */
X
X	*SIO1_MPCC_PSR2 (mpcc) = MPCC_PSR2_1STOP | MPCC_PSR2_8BITS | MPCC_PSR2_ASYNC;
X	*SIO1_MPCC_CCR (mpcc)  = MPCC_CCR_PSCDIV | MPCC_CCR_TCLKO | MPCC_CCR_RCLKIN;
X
X	sio1SetBaudRate (ty, 9600);
X
X	*SIO1_MPCC_ECR (mpcc) = zero;		/* no parity */
X
X	/* set up the receiver */
X	*SIO1_MPCC_RIER (mpcc)  = MPCC_RIER_RDA;	/* int only on data avail */
X	*SIO1_MPCC_RIVNR(mpcc) = INT_VEC_SIO1;  /* Receiver Interrupt Vector */
X	*SIO1_MPCC_RCR (mpcc)   = zero;		/* enable the receiver */
X
X	/* set up the xmitter */
X	*SIO1_MPCC_TIER (mpcc)  = zero;		/* int disabled, until later */
X	*SIO1_MPCC_TIVNR(mpcc) = INT_VEC_SIO1;  /* Transmitter Interrupt Vector */
X	*SIO1_MPCC_TCR (mpcc)   = MPCC_TCR_TEN;	/* enable the xmitter */
X
X	/* set up the serial interface regs. */
X	*SIO1_MPCC_SIER (mpcc)  = zero;		/* disable interrupts */
X	*SIO1_MPCC_SIVNR(mpcc) = INT_VEC_SIO1;  /* Serial Interrupt Vector */
X	*SIO1_MPCC_SICR (mpcc)  = MPCC_SICR_RTSLVL | 
X	                          MPCC_SICR_DTRLVL;	/* Assert DTR and RTS */
X	}
X
X    intUnlock (oldlevel);
X    } 
X
X
X/*******************************************************************************
X*
X* sio1Open - open file to MPCC
X*
X* ARGSUSED
X*/
X
XLOCAL int sio1Open (pTyCoDv, name, mode)
X    TY_CO_DEV *pTyCoDv;
X    char *name;
X    int mode;
X
X    {
X    return ((int) pTyCoDv);
X    }
X
X
X/*******************************************************************************
X*
X* sio1Ioctl - special device control
X*
X* This routine handles baud rate requests, and passes all other requests
X* to tyIoctl.
X*/
X
XLOCAL STATUS sio1Ioctl (pTyCoDv, request, arg)
X    TY_CO_DEV *pTyCoDv; /* device to control */
X    int request;    /* request code */
X    int arg;        /* some argument */
X
X    {
X    STATUS status = OK;
X
X    switch (request)
X	{
X	case FIOBAUDRATE:
X	    sio1SetBaudRate (pTyCoDv, arg);
X	    break;
X
X	default:
X	    status = tyIoctl (&pTyCoDv->tyDev, request, arg);
X	    break;
X	}
X
X    return (status);
X    }
X
X
X/*******************************************************************************
X*
X* sio1Int - handle MPCC interrupt(s)
X*
X* This routine determines which source is generating an interrupt
X* on the MPCC and subsequently passes control to the appropriate
X* interrupt routine.
X*/
X
XLOCAL VOID sio1Int ()
X
X    {
X
X      /* SIO-1 Port 1 */
X    if (*SIO1_MPCC_RSR (SIO1_MPCC_BASE_1) & MPCC_RSR_RDA)
X	sio1RxInt (0);		/* receiver interrupt */
X    else if (*SIO1_MPCC_TSR (SIO1_MPCC_BASE_1) & MPCC_TSR_TDRA)
X	sio1TxInt (0);		/* xmitter interrupt */
X
X      /* SIO-1 Port 2 */
X    if (*SIO1_MPCC_RSR (SIO1_MPCC_BASE_2) & MPCC_RSR_RDA)
X	sio1RxInt (1);		/* receiver interrupt */
X    else if (*SIO1_MPCC_TSR (SIO1_MPCC_BASE_2) & MPCC_TSR_TDRA)
X	sio1TxInt (1);		/* xmitter interrupt */
X
X      /* SIO-1 Port 3 */
X    if (*SIO1_MPCC_RSR (SIO1_MPCC_BASE_3) & MPCC_RSR_RDA)
X	sio1RxInt (2);		/* receiver interrupt */
X    else if (*SIO1_MPCC_TSR (SIO1_MPCC_BASE_3) & MPCC_TSR_TDRA)
X	sio1TxInt (2);		/* xmitter interrupt */
X
X      /* SIO-1 Port 4 */
X    if (*SIO1_MPCC_RSR (SIO1_MPCC_BASE_4) & MPCC_RSR_RDA)
X	sio1RxInt (3);		/* receiver interrupt */
X    else if (*SIO1_MPCC_TSR (SIO1_MPCC_BASE_4) & MPCC_TSR_TDRA)
X	sio1TxInt (3);		/* xmitter interrupt */
X
X      /* SIO-1 Port 5 */
X    if (*SIO1_MPCC_RSR (SIO1_MPCC_BASE_5) & MPCC_RSR_RDA)
X	sio1RxInt (4);		/* receiver interrupt */
X    else if (*SIO1_MPCC_TSR (SIO1_MPCC_BASE_5) & MPCC_TSR_TDRA)
X	sio1TxInt (4);		/* xmitter interrupt */
X
X      /* SIO-1 Port 6 */
X    if (*SIO1_MPCC_RSR (SIO1_MPCC_BASE_6) & MPCC_RSR_RDA)
X	sio1RxInt (5);		/* receiver interrupt */
X    else if (*SIO1_MPCC_TSR (SIO1_MPCC_BASE_6) & MPCC_TSR_TDRA)
X	sio1TxInt (5);		/* xmitter interrupt */
X    }
X
X
X/*******************************************************************************
X*
X* sio1RxInt - handle a receiver interrupt
X*
X* This routine handles an interrupt from the SIO-1 MPCC receiver.
X*/
X
XLOCAL VOID sio1RxInt (channel)
X    FAST int channel;
X
X    {
X    FAST TY_CO_DEV *ty = &sio1Dv[channel];
X
X    /* get character from MPCC and give it to I/O system */
X
X    tyIRd ((TY_DEV_ID) ty, *SIO1_MPCC_RDR (ty->mpcc));
X
X    *SIO1_MPCC_RSR (ty->mpcc) = 0xff;	/* clear the interrupt bit */
X    }
X
X
X/*******************************************************************************
X*
X* sio1TxInt - handle a transmitter interrupt
X*
X* This routine handles an interrupt from the SIO-1 MPCC xmitter.
X* If there is another character to be transmitted, it sends it.  If
X* not, or if a device has never been created, we just
X* disable the interrupt.
X*/
X
XLOCAL VOID sio1TxInt (channel)
X    FAST int channel;
X
X    {
X    FAST TY_CO_DEV *ty = &sio1Dv[channel];
X    FAST char *mpcc = ty->mpcc;
X    char outchar;
X    char zero = 0;
X
X    *SIO1_MPCC_TIER (mpcc) = zero;		/* disable tx interrupts */
X
X    /* get character to output, if any, from i/o system */
X
X    if (tyITx (&ty->tyDev, &outchar) == OK)
X	{
X	*SIO1_MPCC_TSR (mpcc)  = 0xff;		/* clear the interrupt bit */
X	*SIO1_MPCC_TDR (mpcc)  = outchar;		/* output char */
X	*SIO1_MPCC_TIER (mpcc) = MPCC_TIER_TDRA;	/* enable tx interrupt */
X	}
X    }
X
X
X/*******************************************************************************
X*
X* sio1SerialInt - serial interface interrupt level processing
X*
X* This routine handles an interrupt from the MPCC serial interface.
X* Receiver and xmitter interrupts go ththrough different routines.
X* This routine would catch DSR and CTS, except that we don't enable
X* those anyway, so this routine should never be called.
X*
X* ARGSUSED
X*/
X
XLOCAL VOID sio1SerialInt (channel)
X    FAST int channel;
X
X    {
X    char zero = 0;
X
X    *SIO1_MPCC_SIER (sio1Dv[channel].mpcc) = zero;	/* disable serial interrupts */
X    }
X
X
X/*******************************************************************************
X*
X* sio1Startup - transmitter startup routine
X*
X* Output a single character.
X*/
X
XLOCAL VOID sio1Startup (pTyCoDv)
X    FAST TY_CO_DEV *pTyCoDv;	/* ty device to start up */
X
X    {
X    char outchar;
X
X    /* any character to send ? */
X
X    if (tyITx (&pTyCoDv->tyDev, &outchar) == OK)
X	{
X	*SIO1_MPCC_TDR (pTyCoDv->mpcc)  = outchar;		/* output char */
X	*SIO1_MPCC_TIER (pTyCoDv->mpcc) = MPCC_TIER_TDRA;	/* enable tx interrupt*/
X	}
X    }
X
X
X/*******************************************************************************
X*   
X* sio1SetBaudRate - set the MPCC's baud rate on the SIO-1
X*
X* The baud rate is set up assuming that:
X*     1. The local xtal oscillator is the clock.
X*     2. The /3 prescaler is in place (PSCDIV == 1)
X*     3. We're in ASYNC mode (/2).
X*/
X
XLOCAL VOID sio1SetBaudRate (pTyCoDv, rate)
X    TY_CO_DEV *pTyCoDv;		/* device to control */
X    int rate;			/* desired rate */
X
X    {
X    FAST int brdiv = TY_XTAL_FREQ / (rate * 6);
X
X    *SIO1_MPCC_BRDR1 (pTyCoDv->mpcc) = brdiv & 0x00ff;
X    *SIO1_MPCC_BRDR2 (pTyCoDv->mpcc) = (brdiv & 0xff00) >> 8;
X    }
X
X
X
SHAR_EOF
if test 12769 -ne "`wc -c sio1Drv.c`"
then
echo shar: error transmitting sio1Drv.c '(should have been 12769 characters)'
fi
#	End of shell archive
exit 0