|
| $Revision: 1.1.1.1 $
|
#include <asm.h>
	.text
	.even
	.globl	init, _start



| simregs.s 

| define addresses of SIM registers in 68331/332
| adjust the setting of simmcr to reflect modmap bit - here MM=1 !!
	.set rammcr  , 0x00fffb00 
	.set ramtst  , rammcr+2  
	.set rambar  , rammcr+4  
	.set qmcr , 0x00fffc00	   /*  use full 32-bit address for sign extended addresses*/

	.set qtest , qmcr+2        /*  qsm test register */

	.set qilr , qmcr+4         /* qsm interrupt level register*/
	.set qivr , qmcr+5         /* qsm interrupt vector register */

	.set sccr0 , qmcr+0x8       /*   sci control register 0*/ 
	.set sccr1 , qmcr+0xA       /*   sci control register 1*/
	.set scsr , qmcr+0xC        /* sci status register*/
	.set scdr , qmcr+0xE        /* sci data register*/

	.set qpdr , qmcr+0x15       /* qsm port data register*/
	.set qpar , qmcr+0x16       /* qsm pin assignment register*/
	.set qddr , qmcr+0x17       /* qsm data direction register*/

	.set spcr0 , qmcr+0x18      /*  qspi control register 0*/
	.set spcr1 , qmcr+0x1a      /*  qspi control register 1*/
	.set spcr2 , qmcr+0x1c      /*  qspi control register 2*/
	.set spcr3 , qmcr+0x1e      /*  qspi control register 3*/

	.set spsr , qmcr+0x1F       /* qspi status register*/

	.set qrxd , qmcr+0x100      /* qspi receive data buffer start*/
	.set qtxd , qmcr+0x120      /* qspi transmit data buffer start*/
	.set qcmd , qmcr+0x140      /* qspi command buffer start*/
	.set simmcr , 0x00fffa00
	.set simtr , simmcr+2
	.set syncr , simmcr+4    
	.set rsr , simmcr+7
	.set simtre , simmcr+8   
	.set porte , simmcr+0x11
	.set ddre , simmcr+0x15
	.set pepar , simmcr+0x17
	.set portf , simmcr+0x19
	.set ddrf , simmcr+0x1d
	.set pfpar , simmcr+0x1f
	.set sypcr , simmcr+0x21  
	.set picr , simmcr+0x22   
	.set pitr , simmcr+0x24   
	.set swsr , simmcr+0x27
	.set tstmsra , simmcr+0x30
	.set tstmsrb , simmcr+0x32
	.set tstsc , simmcr+0x34
	.set tstrc , simmcr+0x36
	.set creg , simmcr+0x38  
	.set dreg , simmcr+0x3a  
	.set portc , simmcr+0x41
	.set cspar0 , simmcr+0x44
	.set cspar1 , simmcr+0x46
	.set csbarbt , simmcr+0x48
	.set csorbt , simmcr+0x4a
	.set csbar0 , simmcr+0x4c
	.set csor0 , simmcr+0x4e
	.set csbar10 , simmcr+0x74
	.set csor10 , simmcr+0x76

_start:
boot:
	move.w	#0x2700,sr
	move.l	#0x1ffff8,sp

	move.w	#0x09CF,simmcr	/*YFF000 = FFF000 for internal registers*/
	move.b	#0x4,sypcr	/*Busmonitor auf 64 Takte Software-Watchdog aus !*/

	move.w	#0x0057,cspar0	/*Chipselect Pin (PC0-PC2) assignment regs*/
	
	move.w	#0x0006,csbarbt	/* Chipselect base address boot rom*/
	move.w	#0x7d30,csorbt	/* Chipselect Option reg boot rom*/

	move.w	#0x0800,csbar10	/* Chip select fuer DINSEL*/
	move.w	#0x7d30,csor10	/* */
	
	move.b	#0xF7,pepar	/*enables PE3*/
	
/*QSPI-Leitungen aus nach Reset*/
	move.b	#0x7B,qpar	/*assign pins for qspi*/
	move.b	#0x7E,qddr	/*set pins as output-pins*/
	move.b	#0x7b,qpdr	/*I/O-Port data oder Wert der CS-Leitung während des delays after tranfer*/
	
	move.w	#0xfff0,rambar	/*TPURAM-address = 0xFFF000 and enabled*/

/* Systemtakt auf 16.77 MHz einstellen*/

	move.w	syncr,d0	/* syncr in d0*/
	and.w	#0x00FF,d0	/* clear W,X,Y*/
	or.w	#0x8F00,d0	/* set W=1,X=0,Y=001111*/
	move.w	d0,syncr	/* -> 8,389 MHz*/
SYNLOCKED:	
	move.w	syncr,d0	
	andi.w	#0x0008,d0
	tst.w   d0
	beq	SYNLOCKED
	ori.w	#0x4000,syncr	/* set X=1 -> 16,78 MHz*/

/* PC2 - PC0 auf 0 legen -> Motortreiber aus	*/

	move.b	portc,d0	/* Get portc data reg*/
	and.b	#0xf8,d0		/* PC2-PC0 = 0 */
	move.b	d0,portc	/* -> motor drivers off*/

	jsr	init
	jsr	halt		/* should never get here*/